Generally, power transistors formed in VIPower technology, for example, are integrated on the same silicon substrate with components that prevent the collector voltage on the power transistor from reaching potentially dangerous levels.
In particular, when the power transistor is connected with an inductive load, it is necessary to clamp the collector voltage for preventing excessively large voltages from developing on the transistor because of abrupt variations of the current absorbed by the load. A Zener diode (or a plurality of diodes connected in series) is integrated between the collector and the base of the power transistor for an NPN power transistor, as shown in FIG. 1. Whenever the collector-emitter voltage exceeds a certain maximum value, the Zener diode (or diodes) starts conducting. This provides a by-pass path for the current.
Typically, a power transistor is formed by a collector region 1 of a relatively low bulk resistivity on the back of a monocrystalline silicon substrate contacted by a metal collector (COLLECTOR), as shown in FIG. 2.
The lighter doped portion of the substrate 2 has a dopant concentration and thickness so that the transistor can withstand a design breakdown voltage that may be generally between 600V and 1,200V.
On the front side of the substrate is a diffused buried base region 3 doped with a dopant of an opposite type of conductivity to that of the collector region 1. In the buried base region 3 is a buried emitter region 4 of the same type of conductivity as the collector region 1. An epitaxial layer 5 having a thickness ranging between 5 μm and 10 μm is grown over the buried regions 3 and 4.
Base and emitter contact diffusions 6 and 7 are formed with photolithographic and diffusion processes. These contact diffusions extend in depth from the outer surface of the epitaxial layer 5 to the respective base and emitter buried regions 3 and 4. The respective metal contacts BASE and EMITTER are formed on the base and emitter contact diffusions.
A sample layout of a monolithic semiconductor power device formed in VIPower technology is depicted in FIG. 3. The power transistor NPN POWER comprises a control stage DRIVER STAGE and a final stage FINAL STAGE. THe Zener diodes ZENER CHAIN are connected in series between the collector and the base according to the scheme of FIG. 1. A circuit THERMAL COMPENSATION CELL stabilizes the clamp voltage at which the Zener diodes start conducting versus temperature variations.
Outside the active area along the perimeter of the layout, there is an equalization metal ring EQR that is formed to equalize the potential in the whole semiconductor substrate. Typically, this metal layer contacts a superficial region 8 that is heavily doped with a dopant having the same type of conductivity as the collector region 1, hereinafter called the EQR contact region. Between the collector region 1, the substrate 2 and the EQR contact region 8 there is not any P-N junction. Thus, the latter region is practically at the same potential as the collector region. The EQR metal ensures that the whole substrate on which the power transistor is integrated is at a uniform collector potential.
The series of Zener diodes ZENER CHAIN occupy a relatively large silicon surface that increases the cost of the device. It is not possible to reduce the dimensions of the Zener diodes beyond a certain limit because they need to be capable of carrying relatively large currents, without being damaged when the collector voltage exceeds a maximum pre-established threshold.